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Datasheet File OCR Text:

Da ta Sh e et , V 0. 2 2, Fe b. 2 00 4
H YS72 T 320 00 GR (2 56 M B y t e ) H YS72 T 640 01 GR (5 12 M B y t e ) H YS72 T 640 20 GR (5 12 M B y t e )
DDR 2 Reg istered D IMM Modu les
M em or y P r od uc t s
Never stop thinking.
HYS72T32000GR, HYS72T64001GR HYS72T64020GR Preliminary Datasheet Rev. 0.22 (2.04) Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet 256 MByte & 512 MByte Modules PC2-3200R /-4200R /-5300R
* 240-pin Registered 8-Byte ECC Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications * One rank 32Mb x 72, 64Mb x 72 and two ranks 64Mb x 72 organizations * JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with + 1.8 V ( 0.1 V) power supply * Modules built with 256 Mb DDR2 SDRAMs in 60-ball FBGA chipsize packages * Programmable CAS Latencies (3, 4 & 5), Burst Length (4 & 8) and Burst Type. * Auto Refresh and Self Refresh * All inputs and outputs SSTL_1.8 compatible * Performance:
Speed Grade Indicator Component Speed Grade on Module Module Speed Grade Max. Clock Frequency @ CL = 3 Max. Clock Frequency@ CL = 4 & 5 -5 DDR2-400 PC2-3200 200 200 -3.7 DDR2-533 PC2-4200 200 266 -3 DDR2-667 PC2-5300 200 333 MHz MHz Unit
* Re-drive for all input signals using register and PLL devices. * OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) * Serial Presence Detect with E2PROM * Low Profile Modules form factor: 133.35 mm x 30,00 mm (MO-237) * Based on JEDEC standard reference card designs Raw Card "A", "B" and "C".
1.0 Description The INFINEON HYS72T32000GR, HYS72T64020GR and HYS72T64001 are low profile Registered DIMM modules with 30,00 mm height based on DDR2 technology. DIMMs are available in 32M x 72 (256 MByte), 2 x 32M x 72 (512 MByte) and 64M x 72 (512 MByte) organisation and density, intended for mounting into 240 pin connector sockets. The memory array is designed with 256Mbit Double Data Rate (DDR2) Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which provide a proper voltage supply impedance over the whole frequency range of operations as number and values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
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Rainer.Weidlich@Infineon.com
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
1.1 Ordering Information
Type & Partnumber PC2-3200 (DDR2-400): HYS72T32000GR-5-A HYS72T64020GR-5-A HYS72T64001GR-5-A PC2-4200 (DDR2-533): HYS72T32000GR-3.7-A HYS72T64020GR-3.7-A HYS72T64001GR-3.7-A PC2-5300 (DDR2-667): HYS72T32000GR-3-A HYS72T64020GR-3-A HYS72T64001GR-3-A PC2-5300R-44410-A PC2-5300R-44410-B PC2-5300R-44410-C one rank 256 MB Reg. DIMM two ranks 512 MB Reg. DIMM one ranks 512 MB Reg.DIMM 256 Mbit (x8) 256 Mbit (x8) 256 Mbit (x4) PC2-4200R-44410-A PC2-4200R-44410-B PC2-4200R-44410-C one rank 256 MB Reg. DIMM two ranks 512 MB Reg. DIMM one ranks 512 MB Reg.DIMM 256 Mbit (x8) 256 Mbit (x8) 256 Mbit (x4) PC2-3200R-33310-A PC2-3200R-33310-B PC2-3200R-33310-C one rank 256 MB Reg. DIMM two ranks 512 MB Reg. DIMM one ranks 512 MB Reg.DIMM 256 Mbit (x8) 256 Mbit (x8) 256 Mbit (x4) Compliance Code Description SDRAM Technology
Notes: 1. All part numbers end with a place code, designating the silicon die revision. Example: HYS 72T32000GR-5-A, indicating Rev. A dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see section 8 of this datasheet. 2. The Compliance Code is printed on the module label and describes the speed grade, f.e. "PC2-4200R-44410-C", where 4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and "44410" means CAS latency = 4, trcd latency = 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.0 and produced on the Raw Card "C".
1.2 Address Format
Part Number HYS72T32000GR HYS72T64020GR HYS72T64001GRDIMM Density 256 MB 512 MB 512 MB Organization 32Mb x 72 2 x 32Mb x 72 64Mb x 72 Memory Ranks 1 2 1 DDR2SDRAMs (256Mb) 32Mb x 8 (256Mb) 32Mb x 8 (256Mb) 64Mb x 4 # of # of row/bank/ SDRAMs column bits 9 18 18 13/2/10 13/2/10 13/2/11
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
1.3 Components on Modules and RawCard
DIMM Density 256 MB 512 MB 512 MB DRAM components reference datasheet HYB18T256800AC HYB18T256800AC HYB18T256400AC PLL 1:10, 1.8V, CU877 1:10, 1.8V, CU877 1:10, 1.8V, CU877 Register 1:1 25-bit 1.8V SSTU32864 1:2 14-bit 1.8V SSTU32864 1:2 14-bit 1.8V SSTU32864 Raw Card A B C
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component datasheet
1.4 Pin Definition and Function
Pin Name A[12:0] A11, A[9:0] A10/AP BA[1:0] CK0 CK0 RAS CAS WE CS[1:0] CKE[1:0] ODT[1:0] DQ[63:0] Description Row Address Inputs Column Address Inputs 4) Column Address Input for AutoPrecharge SDRAM Bank Selects Clock input
(positive line of differential pair)
Pin Name CB[7:0] DQS[8:0] DM[8:0] / DQS[17:9] DQS[17:0] SCL SDA SA[2:0] VDD VREF VSS VDDSPD RESET NC
Description DIMM ECC Check Bits SDRAM low data strobes SDRAM low data mask/ high data strobes SDRAM differential data strobes Serial bus clock Serial bus data line slave address select Power (+ 1.8 V) I/O reference supply Ground EEPROM power supply Register and PLL control pin 2) No connection
Clock input
(negative line of differential pair)
Row Address Strobe Column Address Strobe Read/Write Input Chip Selects 3) Clock Enable 3) Active termination control lines 1) 3) Data Input/Output
1) Active termination only applies to DQ, DQS, DQS and DM signals 2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the PLL will remain synchronized with the input clock 3) CS1, ODT1 and CKE1 are used on dual rank modules only 4) Column address A11 is used on modules based on x4 organised 256Mb DDR2 components only.
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
1.5 Pin Configuration
PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS RESET NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 PIN# 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Symbol VSS DQ4 DQ5 VSS DM0, DQS9 DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1, DQS10 DQS10 VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2, DQS11 DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3, DQS12 DQS12 VSS DQ30 DQ31 VSS PIN# 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Symbol A4 VDDQ A2 VDD KEY VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE CAS VDDQ CS1 ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 PIN# 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 Symbol VDDQ A3 A1 VDD KEY CK0 CK0 VDD A0 VDD BA1 VDDQ RAS CS0 VDDQ ODT0 NC VDD VSS DQ36 DQ37 VSS DM4, DQS13 DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5, DQS14 DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
Pin Configuration (cont'd)
PIN# 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Symbol VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS VDDQ CKE0 VDD NC NC VDDQ A11 A7 VDD A5
PIN# 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Symbol CB4 CB5 VSS DM8, DQS17 DQS17 VSS CB6 CB7 VSS VDDQ NC, CKE1 VDD NC NC VDDQ A12 A9 VDD A8 A6
PIN# 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Symbol VSS SA2 NC VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL
PIN# 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Symbol NC NC VSS DM6, DQS15 DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7, DQS16 DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
1.6 Pin Locations
Front
p in 1 pin 1 21
64 18 4
65 1 85
120 2 40
Backside
240 pin Modules (MO-237)
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
1.7 Registered DIMM Input/Output Functional Description
Symbol CK0, CK0 Type
Input
Polarity
Function
The system clock inputs. All address and command lines are sampled on the cross point of Cross point the rising edge of CK and the falling edge of CK. An on-board DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. CKE high activates and CKE low deactivates internal clock signals and device input buffers Active High and output drivers of the SDRAMs. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations conActive Low tinue. The input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When both CS[1:0] are high, all register outputs (except CK, ODT and Chip select) remain in the previous state. Active High On-Die Termination control signals Active Low When sampled at the positive edge of the clock, RAS, CAS and WE define the operation to be executed by the SDRAM. Active High Masks write data when high, issued concurrently with input data. Selects which internal SDRAM memory bank is activated During Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to define which bank to precharge. Data and Check Bit Input /Output pins.
CKE[1:0]
Input
CS[1:0]
Input
ODT[1:0] RAS, CAS, WE DM[8:0] BA[1:0]
Input Input Input Input
A[12:0]
Input
-
DQ[63:0], CB[7:0]
I/O
-
DQS[17:0], DQS[17:0]
I/O
The data strobes, associated with one data byte, source with data transfer. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the Cross point data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor maybe connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from the SCL bus line to VDDSPD on the system planar to act as a pull-up. The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the register(s) will be set to low level. The PLL will remain synchronized with the input clock. Power and ground for the DDR SDRAM input buffers and core logic. Reference voltage for the SSTL-18 inputs. Serial EEPROM positive power supply, wired to a separated power pin at the connector which supports from 1.7 Volt to 3.6 Volt.
SA[2:0] SDA SCL RESET VDD, VSS VREF VDDSPD
Input I/O Input Input Supply Supply Supply
Note: CS1, ODT1 and CKE1 are used on dual rank modules only.
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
2.0 Block Diagrams (cont'd) 2.1 One Rank 32M x 72 (256 MByte) DDR2 SDRAM DIMM Module (x8 components) HYS72T32000GR on Raw Card A
RS0 DQS0 DQS0 DM0/DQS9 DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1/DQS10 DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS0 DM2/DQS11 DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3/DQS12 DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8 DM8/DQS17 DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 1:1
R E G I S T E R
NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS
DQS4 DQS4 DM4/DQS13 DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5/DQS14 DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6/DQS15 DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7/DQS16 DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D0
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D1
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D7
Serial PD SCL SDA WP A0 A1 A2
VDDSPD
Serial PD
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
VDD, V DDQ VREF V SS
D0 - D8 D0 - D8 D0 - D8
D8
SA0 SA1 SA2
CS0 * B A 0-BA1 A0 -A12 RAS CAS WE CKE0 ODT0 RESET PCK7 PCK 7
RS0 -> C S : SDRAMs D0-D8 RB A0 -RBA1 -> BA 0-BA1 : SDRAMs D0 -D8 RA0 -RA 12-> A0 -A 12: SDR A Ms D0 -D 8 RR A S -> RAS : SD RAMs D0- D 8 RC AS -> C A S: SD RAMs D0-D8 RW E -> WE : SD RAMs D0-D8 RCK E0 -> CKE : SDR A D0-D8 RODT0 -> ODT 0: SDRAMs D0-D8
CK0
CK 0 P L L OE
PCK0-PCK6,PCK8,PCK9 PCK0-PCK6,PCK8,PCK9 PCK7-> CK : Register PCK7 > CK : Register
CK : SDRAMs D0-D8 CK : SDRAMs D0-D8
RESET
RST
Notes: 1. DQ-to-I/O wiring may be changed within a byte 2. Unless otherwise noted, resistor values are 22 Ohms
*) CS0 connects to DCS and VDD connects to CSR on the Registers
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
Block Diagrams (cont'd) 2.2 64M x 72 (512 MByte) two rank DDR2 SDRAM DIMM Modules (x8 components) HYS72T64020GR on Raw Card B
RS1 RS0 DQS0 DQS0 DM0/DQS9 DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1/DQS10 DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS0 DM2/DQS11 DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3/DQS12 DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8 DM0/DQS17 DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS
DQS4 DQS4 DM4/DQS13 DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5/DQS14 DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6/DQS15 DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7/DQS16 DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D9
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D13
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D10
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D14
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D2
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D11
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D15
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D12
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D16
VDDSPD
Serial PD
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1:2
R E G I S T E R
D8
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
VDD, V DDQ D17 VREF V SS Serial PD SCL WP A0 A1 A2
D0 - D17 D0 - D17 D0 - D17
SDA
CS0 * CS1 * B A 0-BA1 A0 -A12 RAS CAS WE CKE0 CKE1 ODT0 ODT1 RESET PCK7 PCK 7
RS0 -> C S : SDRAMs D0-D8 RS1 -> C S : SDRAMs D9-D17 RB A0 -RBA1 -> B A 0-BA1 : SDRAMs D0-D17 RA0 -RA 12-> A0 -A 12: SDR A Ms D0-D17 RR A S -> RAS : SD RAMs D0-D17 RC AS -> C A S: SD RAMs D0-D17 RW E -> WE : SD RAMs D0-D17 RCK E0 -> CKE :SDRAMs D0-D8 RCK E1 -> CKE :SDRAMs D9-D17 RODT0 -> ODT : SDRAMs D0-D8 RODT1 -> ODT : SDRAMs D9-D17
SA0 SA1 SA2 CK 0 CK 0 P L L OE PCK0-PCK6, PCK8,PCK9 PCK0-PCK6, PCK8,PCK9 CK : SDRAMs D0-D17 CK : SDRAMs D0-D17
RESET
: PCK7 -> CK Register PCK7 > CK : Register
RST
DQ-to-I/O wiring may be changed within a byte DQ/DQS/DQS, adress and control resistors are 22 Ohms
*) CS0 connects to CRS, CS1 connects to CSR on a Register. CS1 connects to DCS and CS0 connects to CSR on another Register. RESET, PCK7 and PCK7 connect to bother Registers. Other signals connect to one of two Registers.
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Block Diagrams (cont'd) 2.3 One Rank 64M x 72 (512 MByte) DDR2 SDRAM DIMM Modules (x4 components)
HYS72T64001GR on Raw Card C
VSS RS0 DQS0 DQS0
DM CS DQS DQS
DQS9 DQS9
DM
DQ0 DQ1 DQ2 DQ3 DQS1 DQS0
I/O I/O I/O I/O
0 1 2 3
D0 DQS10 DQS10
DQ4 DQ5 DQ6 DQ7
CS DQS DQS
I/O I/O I/O I/O
0 1 2 3
D9
DM
DQ8 DQ9 DQ10 DQ11 DQS2 DQS2
CS DQS DQS
DM
I/O I/O I/O I/O
0 1 2 3
D1 DQS11 DQS11
DQ12 DQ13 DQ14 DQ15
CS DQS
DQS
I/O I/O I/O I/O
0 1 2 3
D10
DM
DQ16 DQ17 DQ18 DQ19 DQS3 DQS3
CS DQS DQS
DM
I/O I/O I/O I/O
0 1 2 3
D2 DQS12 DQS12
DQ20 DQ21 DQ22 DQ23
CS DQS
DQS
I/O I/O I/O I/O
0 1 2 3
D11
DM
DQ24 DQ25 DQ26 DQ27 DQS4 DQS4
CS DQS DQS
DM
I/O I/O I/O I/O
0 1 2 3
D3 DQS13 DQS13
DQ28 DQ29 DQ30 DQ31
CS DQS
DQS
I/O I/O I/O I/O
0 1 2 3
D12
DM
DQ32 DQ33 DQ34 DQ35 DQS5 DQS5
CS DQS DQS
DM
I/O I/O I/O I/O
0 1 2 3
D4 DQS14 DQS14
DQ36 DQ37 DQ38 DQ39
CS DQS
DQS
I/O I/O I/O I/O
0 1 2 3
D13
DM
DQ40 DQ41 DQ42 DQ43 DQS6 DQS6
CS DQS DQS
DM
I/O I/O I/O I/O
0 1 2 3
D5 DQS15 DQS15
DQ44 DQ45 DQ46 DQ47
CS DQS
DQS
I/O I/O I/O I/O
0 1 2 3
D14
DM
DQ48 DQ49 DQ50 DQ51 DQS7 DQS7
CS DQS DQS
DM
I/O I/O I/O I/O
0 1 2 3
D6 DQS16 DQS16
DQ52 DQ53 DQ54 DQ55
CS DQS
DQS
I/O I/O I/O I/O
0 1 2 3
D15
DM
DQ56 DQ57 DQ58 DQ59 DQS8 DQS8
CS DQS DQS
DM
I/O I/O I/O I/O
0 1 2 3
D7 DQS17 DQS17
CS DQS DQS
DQ60 DQ61 DQ62 DQ63
CS DQS
DQS
I/O I/O I/O I/O
0 1 2 3
D16
DM
DM
CB0 CB1 CB2 CB3
I/O I/O I/O I/O
0 1 2 3
D8
CB4 CB5 CB6 CB7 Serial PD
CS DQS
DQS
I/O I/O I/O I/O
0 1 2 3
D17
VDDSPD SDA
Serial PD
CS0 * B A 0-BA1 A0 -A12 RAS CAS WE CKE0 ODT0 RESET PCK7 PCK 7
1:2
R E G I S T E R
RST
RS0 -> C S : SDRAMs D0-D17 RB A0 -RBA1 -> BA 0-BA1 : SDRAMs RA0 -RA 12-> A0 -A 12: SDR A Ms D0-D17 RRA S -> RAS : SD RAMs D0-D17 RCAS -> C A S: SD RAMs D0-D17 RW E -> WE : SD RAMs D0-D17 RCK E0 -> CKE : SDRAMs D0-D17 RODT0 -> ODT : SDRAMs D0-D17
SCL WP A0 A1 A2
VDD, V DDQ VREF V SS
D0 - D17 D0 - D17 D0 - D17 CK : SDRAMs D0-D17 CK : SDRAMs D0-D17
SA0 SA1 SA2
CK 0 CK 0
P L L OE
PCK0-PCK6, PCK0-PCK6,
PCK8,PCK9 PCK8,PCK9
*) CS0 connects to DCS of Register 1 and CSR of Register 2, CSR of Register 1 and DCS of Register 2 connects to VDD **) RESET, PCK7 and PCK7 connet to both Registers. Other signals connect to one of two Registers.
RESET
PCK7 -> CK : Register PCK7 > CK : Register
DQ-to-I/O wiring may be changed within per nibble Unless otherwise noted, resistor values are 22 Ohms
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3.0 Absolute Maximum Ratings
Parameter Symbol Limit Values min. Voltage on any pins relative to VSS Voltage on VDD relative to VSS Voltage on VDD Q relative to VSS Storage temperature range VIN, VOUT VDD VDDQ TSTG - 0.5 - 1.0 - 0.5 -55 max. 2.3 2.3 2.3 +100
o
Unit
V V
C
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3.1 Operating Temperature Range
Parameter Symbol Limit Values min. DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range TOPR TCASE 0 0 max. +55 +95
o o
Unit
Notes
C C 1-4
1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. Within the DRAM Component Case Temperature range all DRAM specification will be supported. 3. Above 85oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85oC case temperature before initiating self-refresh operation.
3.2 Supply Voltage Levels and DC Operating Conditions
Parameter Symbol min. Device Supply Voltage Output Supply Voltage Input Reference Voltage EEPROM Supply Voltage DC Input Logic High DC Input Logic Low In / Output Leakage Current
1 2 3
Limit Values nom. 1.8 1.8 0.5 x VDDQ - - - - max. 1.9 1.9 0.51 x VDDQ 3.6 VDDQ + 0.3 VREF - 0.125 5
Unit
Notes
VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7 VREF + 0.125 - 0.30 -5
V V V V V V A
1) 2)
3)
Under all conditions, VDDQ must be less than or equal to VDD Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise variations in VDDQ. For any pin on the DIMM connector under test input of 0 V VIN VDDQ + 0.3 V.
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4.0 IDD Specifications and Conditions 4.1 256MByte Registered Module HYS72T32000GR (one rank, nine components x8)
256 MByte HYS72T32000GR Symbol Parameter / Condition IDD0 Operating Current IDD1 IDD2P IDD2N IDD2Q
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current
PC2-3200 "-5" max. 700 745 286 502 430 367 286 520 790 880 970 304 36 1375
PC2-4200 "-3.7" max. 828 873 369 657 558 477 369 648 963 1098 1098 387 36 1548
PC2-5300 "-3" max. 957 1002 453 822 687 597 867 777 1137 1317 1227 471 36 1722 Unit Note 1 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1 1 1 1 1 1 1 1 1 1 1 1 1
IDD3P(0) Active PD Standby Current IDD3P(1) LP Active PD Standby Current IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL.
4.2 512 MByte Registered Module HYS72T64020GR (two ranks, eighteen components x8)
512 MByte HYS72T64020GR Symbol Parameter / Condition IDD0 Operating Current IDD1 IDD2P IDD2N IDD2Q
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current
PC2-3200 "-5" max. 854 899 440 872 728 602 440 908 944 1034 1126 476 72 1529
PC2-4200 "-3.7" max. 1021 1066 562 1138 940 778 562 1120 1156 1291 1291 598 72 1741
PC2-5300 "-3" max. 1190 1235 686 1424 1154 974 686 1334 1370 1550 1460 722 72 1955 Unit Note mA 1, 2 mA mA mA mA mA mA mA mA mA mA mA mA mA
1, 2 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 2 1, 2 1, 2 1, 3 1, 3 1, 2
IDD3P(0) Active PD Standby Current IDD3P(1) LP Active PD Standby Current IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
4.3 512 Mbyte Registered Module HYS72T64001GR (one rank, eighteen components x4)
512 MByte HYS72T64001GR Symbol Parameter / Condition IDD0 Operating Current IDD1 IDD2P IDD2N IDD2Q
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current
PC2-3200 "-5" max. 1268 1358 440 872 728 602 440 908 1448 1628 1808 476 72 2618
PC2-4200 "-3.7" max. 1480 1570 562 1138 940 778 562 1120 1750 2020 2020 598 72 2920
PC2-5300 "-3" max. 1694 1784 686 1424 1154 974 686 1334 2054 2414 2234 722 72 3224 Unit Note 1 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1 1 1 1 1 1 1 1 1 1 1 1 1
IDD3P(0) Active PD Standby Current IDD3P(1) LP Active PD Standby Current IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL.
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4.4 IDD Measurement Conditions
Symbol Parameter/Condition Operating Current - One bank Active - Precharge tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD), CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current - One bank Active - Read - Precharge IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD),tRCD = tRCD(IDD),AL = 0, CL = CL(IDD); CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCK(IDD); Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD0 IDD1 IDD2P IDD2N IDD2Q
CKE is LOW; Other control IDD3P(0) Active Power-Down Current: All banks open; tCK = tCK(IDD),(Fast Power-down Exit); and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "0" CKE IDD3P(1) Active Power-Down Current: All banks open; tCK = tCK(IDD),(Slow is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "1" Power-down Exit);
IDD3N IDD4R IDD4W IDD5B IDD5D IDD6
Active Standby Current: All banks open; tCK = tCK(IDD); tRAS = tRASmax(IDD); tRP = tRP(IDD),CKE is HIGH; CS is high between valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Auto-Refresh Current: tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Auto-Refresh Current: tCK = tCK(IDD), Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Self-Refresh Current: CKE 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max. All Bank Interleave Read Current: 1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL=CL(IDD), AL = tRCD(IDD) -1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is high between valid commands, Address bus inputs are STABLE during DESELECTS; Data bus is SWITCHING. 2. Timing pattern: - DDR2 -400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D - DDR2 -533: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D - DDR2 -667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D 3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
IDD7
Notes: 1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 2. Definitions for IDD: LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min. STABLE is defined as inputs are stable at a HIGH or LOW level. FLOATING is defined as inputs are VREF = VDDQ / 2. SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes. 3. IDD1, IDD4R, and IDD7 current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH. 3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 4. RESET signal is high for all currents, except for IDD6 "Self Refresh". 5. All current measurements includes Register and PLL current consumption.
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4.5 IDD Measurement Conditions (cont'd)
For testing the IDD parameters, the following timing parameters are used:
-5 PC2-3200 3-3-3 CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval CL(IDD) tCK(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tRASmin(IDD) tRASmax(IDD) tRP(IDD) tRFC(IDD) tREFI 3 5 15 60 7.5 45 70000 15 75 7.8 -3.7 PC2-4200 4-4-4 4 3.75 15 60 7.5 45 70000 15 75 7.8 -3 PC2-5300 4-4-4 4 3 12 57 7.5 45 70000 12 75 7.8 tCK ns ns ns ns ns ns ns ns s
Unit
Parameter
Symbol
4.5 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & A2 in the EMRS(1) a "week" or "strong" termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tri-state or driving "0" or "1", as long a ODT is enabled during a given period of time.
ODT current per terminated pin:
EMRS(1) State Enabled ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING. A6 = 0, A2 = 1 IODTO A6 = 1, A2 = 0 A6 = 0, A2 = 1 IODTT A6 = 1, A2 = 0 5 6 7.5 mA/DQ 2.5 10 3 12 3.75 15 mA/DQ mA/DQ min. 5 typ. 6 max. 7.5 Unit mA/DQ
note: For power consumption calculations the ODT duty cycle has to be taken into account
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5.0 Electrical Characteristics & AC Timings
5.1 AC Timing Parameter by Speed Grade (Component level data, for reference only) -5 DDR2 -400
Min Max + 600 + 500 0.55 0.55 - 600 - 500 0.45 0.45
Symbol
Parameter
-3.7 DDR2 -533
Min -500 -450 0.45 0.45 Max +500 +450 0.55 0.55
-3 DDR2 -667
Min -450 -400 0.45 0.45 Max +450 +400 0.55 0.55
Unit
tAC tCH tCL tHP tCK tIS tIH tDS tDH tIPW tHZ
DQ output access time from CK / CK
ps ps tCK tCK
tDQSCK DQS output access time from CK / CK
CK, CK high-level width CK, CK low-level width Clock Half Period Clock cycle time CL = 3 CL = 4 & 5
min. (tCL, tCH) 5000 5000 600 600 400 400 0.6 0.35 2*tACmin tACmin 8000 8000 tACmax tACmax tACmax 350 450
min. (tCL, tCH) 5000 3750 600 600 350 350 0.6 0.35 2*tACmin tACmin 8000 8000 tACmax tACmax tACmax 300 400
min. (tCL, tCH) 5000 3000 tbd. tbd. 300 300 0.6 0.35 2*tACmin tACmin 8000 8000 tACmax tACmax tACmax 250 350 WL +0.25 0.60 1.1 0.60 70000 tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns ns ps ps ps ps ps ps tCK tCK ps ps ps ps ps
Address and control input setup time Address and control input hold time DQ and DM input setup time DQ and DM input hold time Control and Addr. input pulse width (each input)
tDIPW DQ and DM input pulse width (each input)
Data-out high-impedance time from CK / CK
tLZ(DQ) DQ low-impedance from CK / CK tLZ(DQS) DQS low-impedance from CK / CK tDQSQ tQHS tQH
DQS-DQ skew (for DQS & associated DQ signals) Data hold skew factor Data Output hold time from DQS
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 45 60 75
WL +0.25 0.60 1.1 0.60 70000 -
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 45 60 75
WL +0.25 0.60 1.1 0.60 70000 -
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0.35 0.40 0.9 0.40 45 57 75
tDQSS Write command to 1st DQS latching transition tDQSL,H DQS input low (high) pulse width (write cycle) tDSS tDSH tMRD tWPRE tRPRE tRAS tRC tRFC
DQS falling edge to CLK setup time (write cycle) DQS falling edge hold time from CLK (write cycle) Mode register set command cycle time Write preamble
tWPST Write postamble
Read preamble
tRPST Read postamble
Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
Symbol
Parameter
-5 DDR2 -400
Min Max 12 7.8 3.9
-3.7 DDR2 -533
Min 15 15 7.5 2 15 WR+tRP 7.5 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH Max 12 7.8 3.9
-3 DDR2 -667
Min 12 12 7.5 2 15 WR+tRP 7.5 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH Max 12 7.8 3.9
Unit
tRCD tRP tRRD tCCD tWR tDAL tRTP tXARD tXARDS tXP
Active to Read or Write delay (with and without Auto-Precharge) delay Precharge command period Active bank A to Active bank B command (1k page size) CAS A to CAS B Command Period Write recovery time
15 15 7.5 2 15
ns ns ns tCK ns tCK ns ns tCK tCK tCK tCK ns tCK ns ns s
Auto precharge write recovery + precharge time WR+tRP 10 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH -
tWTR Internal write to read command delay
Internal read to precharge command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to read command (slew exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect)
tXSRD Exit Self-Refresh to read command tXSNR Exit Self-Refresh to non-read command tCKE tOIT
CKE minimum high and low pulse width OCD drive mode output delay
tDELAY Minimum time clocks remain ON after CKE asynchronously drops low
Periodic tREFI Average Interval Refresh 0 C - 85 C 85oC - 95oC
o o
1. For details and notes see the relevant INFINEON component datasheet 2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also effect the SPD code for these parameters.
5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition min. 2 DDR2-400/533 DDR2-667 tAC(min) tAC(min) tAC(min) + 2 ns 2.5 tAC(min) tAC(min) + 2 ns 3 8 max. 2 tAC(max) + 1 ns tAC(max) + 0.7 ns 2 tCK + tAC(max) + 1 ns 2.5 tAC(max) + 0.6 ns 2.5 tCK + tAC(max) + 1 ns Units
tAOND tAON
ODT turn-on delay ODT turn-on
tCK ns ns tCK ns ns tCK tCK
tAONPD ODT turn-on (Power-Down Modes) tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-off delay ODT turn-off ODT turn-off delay (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
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6.0 Serial Presence Detect Codes for Registered DIMM Modules
Byte# Description Note: "-5 " := DDR2-3200 (DDR2-400) "-3.7" := DDR2-4200 (DDR2-533) "-3 " := DDR2-5300 (DDR2-667) Speed Grade SPD Entry Value HYS72T32000GR Hex Value HYS72T64020GR HYS72T64001GR 0B 60 04 04 80
0 1 2 3 4 5 6 7 8 9
Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Ranks, Package and Height Module Data Width Not used Module Interface Levels Min. Clock Cycle Time at CAS Latency = 5
10
SDRAM Access Time from Clock at CL = 5
11 12 13 14 15 16 17 18 19 20 21 22 23
DIMM Configuration Type Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Not used Burst Length Supported Number of SDRAM Banks Supported CAS Latencies Not used DIMM Type Information SDRAM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 4
24
SDRAM Access Time from Clock at CL = 4
25 26 27 28 29 30 31
Min. Clock Cycle Time at CAS Latency = 3 SDRAM Access Time from Clock at CL = 3 Minimum Row Precharge Time (tRP) Minimum Row Act. to Row Act. Delay (tRRD) Minimum RAS to CAS Delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Density (per rank)
all all all all all all all all all -5 -3.7 -3 -5 -3.7 -3 all all all all all all all all all all all all -5 -3.7 -3 -5 -3.7 -3 all all -5 & -3.7 -3 all -5 & -3.7 -3 all all
128 256 DDR2-SDRAM 13 10 / 11 1/2 x72 not used SSTL_1.8 5 ns 3.7 ns 3 ns 0.6 ns 0.5 ns 0.45 ns ECC 7.8 s / SR x8, x4 x8, x4 not used 4&8 4 5, 4, 3 not used Reg. DIMM see note 1 incl. weak driver 5 ns 3.7 ns 3 ns 0.6 ns 0.5 ns 0.45 ns 5 ns 0.6 ns 15 ns 12 ns 7.5 ns 15 ns 12 ns 45 ns
0A 60
08 08
40
80 08 08 0D 0A 61 48 00 05 50 3D 30 60 50 45 02 82 08 08 00 0C 04 38 00 01 00 01 50 3D 30 60 50 45 50 60 3C 30 1E 3C 30 2D 40
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Byte#
Description Note: "-5 " := DDR2-3200 (DDR2-400) "-3.7" := DDR2-4200 (DDR2-533) "-3 " := DDR2-5300 (DDR2-667)
Speed Grade
SPD Entry Value HYS72T32000GR
Hex Value HYS72T64020GR HYS72T64001GR B6 tbd. tbd.
32
Address and Command Setup Time (tIS)
33
Address and Command Hold Time (tIH)
34
Data Input Setup Time (tDS)
35
Data Input Hold Time (tDH)
36 37 38 39 40 41 42 43 44
Write Recovery Time (tWR) Internal Write to Read Command delay (tWTR) Internal Read to Precharge delay (tRTP) Not used Extension of Byte 41 tRC and Byte 42 tRFC Minimum Core Cycle Time (tRC) Min. Auto Refresh Command Cycle Time (tRFC) Maximum Clock Cycle Time tck Max. DQS-DQ Skew (tDQSQmax.)
-5 -3.7 -3 -5 -3.7 -3 -5 -3.7 -3 -5 -3.7 -3 all -5 -3.7 & -3 all all -5 & -3.7 -3 all all -5 -3.7 -3 -5 -3.7 -3
0.60 ns 0.50 ns 0.45 ns 0.60ns 0.50 ns 0.45ns 0.40 ns 0.35 ns 0.30 ns 0.40 ns 0.35 ns 0.30 ns 15 ns 10 ns 7.5 ns 7.5 ns not used 60 ns 57 ns 75 ns 8 ns 0.35 ns 0.30 ns 0.25 ns 0.45 ns 0.40 ns 0.35 ns 15.0 s see note 1 Revision 1.0 7D tbd. tbd.
45
Read Data Hold Skew Factor (tQHS)
46 47-61 62 63
PLL Relock Time Reserved for "Delta Temperature in SPD" SPD Revision Checksum for Bytes 0 - 62
-5 -3.7 -3
64 Manufacturers JEDEC ID Code INFINEON 65-71 Not used not used 72 Module Assembly Location 73-90 Module Part Number 91-92 Module Revision Code 93-94 Module Manufacturing Date Year/Week Code 95-98 Module Serial Number Serial Number 99-127 Manufacturer's Specific Data blank 128-255 Open for Customer use blank Note 1 : Will be used for future SPD Code Revisions. For details of "Delta Temperature in SPD" see JEDEC ballot JC42.5 Item # 1468.
60 50 45 60 50 45 40 35 30 40 35 30 3C 28 1E 1E 00 00 3C 39 4B 80 23 1E 19 2D 28 23 0F 00 10 7E tbd. tbd. C1 00 XX XX XX XX XX FF
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
7.0 Package Outline 7.1 Raw Card A Module Package DDR2 Registered DIMM Modules Raw Card A one physical rank, 9 components x8 organised
133.35 + 0.15
2.7 max.
Front View
Register PLL
30.0.
4.0
pin 1 5,175 63,0
64
65 55,0 5.0
120 5,175
1.27 + 0.1
PCB warpage 0.40
Backside View
pin 121 10.0 184 185 240
17.80
3
3
Detail of Contacts A 0.20 + 0.15 2.50 + 0.20 -
Detail of Contacts B 5.0 0.75R 3.8 typ. 1.5 2.5
0.8 + 0.05
1.0
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
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7.2 Raw Card B
Module Package DDR2 Registered DIMM Modules Raw Card B two one physical rank, 18 components x8 organised
1 3 3.3 5 + 0.15
4.0 m a x.
Front View
Register PLL
4 .0 30.0.
p in 1 5,1 75 6 3,0
64
65 55 ,0 5.0
1 20 5 ,1 7 5
1 .27 + 0.1
PCB warpage 0.40
Backside View
pin 1 21 10.0 1 84 185 240
17.80
3
Register
3
D e ta il of C on tac ts A 0.20 + 0.15 2.50 + 0.20 -
D e tail o f C o nta cts B 5 .0 0 .75 R 3.8 typ. 1 .5 2.5
0 .8 1 .0
+ 0.05 -
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
INFINEON Technologies
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
7.3 Raw Card C
Module Package DDR2 Registered DIMM Modules Raw Card C one physical rank, 18 components x4 organised
1 3 3.3 5 + 0.15
4.0 m a x.
Front View
Register PLL
4 .0 30.0.
p in 1 5,1 75 6 3,0
64
65 55 ,0 5.0
1 20 5 ,1 7 5
1 .27 + 0.1
PCB warpage 0.40
Backside View
pin 1 21 10.0 1 84 185 240
17.80
3
Register
3
D e ta il of C on tac ts A 0.20 + 0.15 2.50 + 0.20 -
D e tail o f C o nta cts B 5 .0 0 .75 R 3.8 typ. 1 .5 2.5
0 .8 1 .0
+ 0.05 -
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
INFINEON Technologies
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HYS72Txx0xxGR Registered DDR2 SDRAM-Modules
8.0 Nomenclature (Modules & Components)
8.1 DDR2 DIMM Modules
1 Example:
1 2 3
INFINEON Prefix Module Data Width DRAM Technology
2 64
3 T
4 64
5 0
6 2
7 8 9
7 0
8 G
9 R
10 -5
11 -A
0 = standard 2 = dual die package G= BGA components R = Registered DIMMs U = Unbuffered DIMMs DL = Small Outline DIMMs -5 = PC2-3200 (DDR2-400) -3.7 = PC2-4200 (DDR2-533) -3 = PC2-5300 (DDR2-667) A = 1st Generation B = 2nd Generation C = 3rd Generation
HYS
HYS for DIMM Modules 64 = Non-ECC Modules 72 = ECC Modules T = DDR2 32 = 32 Mb 64 = 64 Mb 128 = 128 Mb 256 = 256 Mb 0 = first generation 0 = One Rank 2 = Two Ranks
Product Variations Package Module Type
4
Memory Density per I/O
10
Speed Grade
5
Raw Card Generation Number of Memory Ranks
11
Die Revision
6
Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes.
8.2 DDR2 Memory Components
1 Example: HYB
2 18
3 T
4 256
5 40
6 0
7 A
8 C
9 -5
1 2
INFINEON Component Prefix Power Supply Voltage
HYB for DRAM Components 18 = 1.8 V Power Supply
6 7
Product Variations Die Revision
0 = standard A = 1st Generation B = 2nd Generation C = 3rd Generation C = BGA package F = BGA package (lead and halogen free) -5 =...DDR2-400 -3.7 =.DDR2-533 -3 =...DDR2-667
3
DRAM Technology
T = DDR2 256 = 256 Mb 512 = 512 Mb 1G = 1024Mb 40 = x4, 4 data in/outputs 80 = x8, 8 data in/outputs 16 = x16, 16 data in/outputs
8 9
Package Type
4
Memory Density
Speed Grade
5
Memory Organisation
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